The present invention generally relates to a signal processing device, and in particular to a data synchronizing (sync) signal detecting device with an improved sync signal detection rate which can detect a sync signal even in the case where a sync signal section has a data discrimination error.
An example of the conventional sync signal detecting device will be explained with reference to FIGS. 9 and 10.
A magnetic disk device is referred to as an example for explaining the prior art.
FIG. 9 shows an example of a recording format of a conventional magnetic disk device.
The data includes an identity (ID) section and a data section for each sector making up a unit storage area. The ID section and the data section each includes a phase-locked oscillator (PLO) sync field 91 for pull-in of a PLL (phase-locked loop), a sync byte (sync signal) 92 for detecting the starting point of the ID (address information) or the data and producing a demodulation timing signal of the code, an ID field for recording/reproducing ID information actually or a data field 93 for recording/reproducing the data, and a cyclic redundancy check (CRC) or an error correcting code (ECC) 94 for detecting or correcting an error.
Also, a gap 95 making up a pattern for absorbing various delay times is interposed between the ID section and the data section or between sectors.
It is well known that accurate detection of the sync signal 92 is very important for subsequent code demodulation of the ID and the data field 93.
Specifically, even in the case where the code-demodulated data in the ID or data field 93 has a very satisfactory error rate, an error in detecting the sync signal 92 (which is normally several bytes) will subsequently result in an incorrect code demodulation of several ten to several hundred bytes of the ID or the data field 93. The entire ID or data field 93 may develop an error as a result, thereby causing an extreme deterioration in the overall error rate.
More specifically, a sync signal detection system having a configuration as shown in FIG. 10 equalizes the incoming data 4 by an equalizer 1, and applies an equalized signal 5 to a data sync signal detector, which matches equalized signal 5 with a predetermined sync pattern 12, and if they coincide with each other, a sync signal is detected.
The sync signal detection will fail if the sync signal field 92 develops even a single bit of data error, which will result in an erroneous ID or data field 93. Specifically, if the sync signal field develops a permanent bit drop-off due to a defect of a medium or the like, the data for a sector cannot be correctly reproduced.
In view of this, several methods have been proposed for improving the detection rate of the sync signal.
An example is JP-A-58-169341 which discloses a technique for improving the reliability of sync signal detection in the case where the ratio between data words and code words is 0.5.
This method is considered effective especially when the ratio between data words and code words is 0.5. Due to the low ratio between data words and code words, however, the number of bits of the code actually recorded or reproduced is twice as many as the number of bits of the data. This method, therefore, is disadvantageous with respect to recording density. Further, this method does not include configuration using the high discrimination performance of a Viterbi decoder.
Also, JP-A-5-334810 discloses a technique of improving the reliability of the sync signal detection in the case where the transmission path has a transmission characteristic of partial response type and the sync pattern is coded in blocks.
This technique is intended to achieve highly reliable sync signal detection using multi-Value data as an input to a sync signal detection circuit. This configuration, however, is expected to increase the circuit size.
Further, JP-A-7-182786 discloses a technique for improving the reliability of sync signal detection in the case where the system has a data channel of PR4 (partial response class 4).
This technique is intended to improve the reliability of sync signal detection by adding a pattern with a predicted error to a sync pattern to be matched. This technique is also expected to increase the circuit size due to an increased number of sync patterns to be matched.
The above-mentioned two techniques include a sync signal detection circuit independent of a data discriminator, and therefore the detection performance of the sync signal is determined regardless of the discrimination performance of the data discriminator.
Even when the performance of the data discriminator is improved in the future, therefore, the sync signal detection performance will remain unchanged or rather will be deteriorated relatively.
As a specific example, even though the data discrimination performance can be improved by modifying the configuration of the data discriminator from a Viterbi decoder circuit of PR4 (partial response class 4) to a most-likelihood decoder circuit of EPR4 (expanded partial response class 4), the sync signal detection performance remains unchanged.
The result is that the sync signal detection performance appears to have deteriorated by an amount equivalent to a particular improvement in data discrimination performance.
Another solution may be to use the improvement in the data discrimination performance for improving the recording density and, for this purpose, to use an input signal of a deteriorated quality (such as a lower signal-to-noise ratio). In such a case, however, the sync signal detection performance may appear to have deteriorated by more than an amount equivalent to the improvement in the data discrimination performance.
Assume that the sync signal at the beginning of the data is erroneously detected, or assume, for example, that it cannot be detected at the right position or is detected at a wrong position. Then, the erroneous detection of the sync signal causes an error in the subsequent code demodulation of all the data of several hundred bytes, thereby leading to a technical problem of an extremely deteriorated overall error rate.